Re: Verilog/ASIC development support is insufficient in git , help!

From: Kevin Ballard <kevin@sb.org>
Date: May 11, 2008, 05:33 UTC
Message-ID: <F975216F-9B61-41FF-A7FE-3D7EF09D137B@sb.org>
In-Reply-To: <83EE186A7AF140179C6C73B367471EC7@justinuTop>

On May 11, 2008, at 12:29 AM, Justin Leung wrote:

Show 21 quoted lines

> Hi Kevin,
>
> The ability of inter-user (designer-verifier) code sync'ing without  
> letting the incomplete or incompatible RTL code to propagate to the  
> main build stream is going to facilitate the design flow and  
> efficiency .
>
> The ability of local revision control means that no more over  
> writing of design files until commit .
>
> I think these 2 things will really buy us alot .
>
> Justin
>
>> Honestly, it sounds like SVN is actually a good fit here. Just  
>> because git is awesome for many things does not mean it is the end- 
>> all-be-all  of version control systems. SVN still has its place as  
>> the last true centralized system. Given your constraints and  
>> workflow, why do you  think git is better than SVN?
>>
>> -Kevin Ballard

But they come at an expense - no more linear revision numbers, more complex commands, etc. You can't have it both ways.

You could always use a main SVN repo and then use git-svn to maintain your own private git repos, do all the code syncing you want there, and then push it back to SVN when you want to send it back to the main build stream. If you go this route, be careful to maintain a linear history on the branch that tracks the SVN repo, as SVN cannot handle merges the way git can. You'll want to either do rebasing or squashed merges (to avoid multiple parents).

-Kevin Ballard

-- 
Kevin Ballard
http://kevin.sb.org
kevin@sb.org
http://www.tildesoft.com