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Re: Verilog/ASIC development support is insufficient in git , help!

From
JLJustin Leung <jleung@redback.com>
Date
May 12, 2008, 18:51 UTC
Message-ID
<482891C6.1050607@redback.com>
In-Reply-To
<46d6db660805110221y1207974dt3be709e1b67cf3d6@mail.gmail.com>
Hi Christian,
 I personally have no problem dealing without revision numbers .
I merely used them directly .
However, I think I gotta admit that this is a world more than just us .

There's an obvious reason why Windows and MS are still standing, and IE is still the market holder :

we are the minority ..  a lot of people just care to get the work done .

surely i felt defeated, but one lesson to know is that the interface is very important for beginners ;

and a simplified numbering scheme is really what the managers/VPs are looking for to avoid rookie mistakes .

Thanks for the support tho =) I know i m not alone

 Justin
Christian MICHON wrote:
Show 27 quoted lines
> I'm an ASIC designer too.
> this is unimportant: if they want to track a specific release of a
> file, it's better to look at what was the file's content from this cut
> to that cut.
> just use gitk and git-gui: almost all can be done with these two
> graphical tools.
>
> for linear development, yes. but when we were requested to perform
> maintenance on a specific old cut, this was becoming a nightmare.
> gitk, git-gui: two commands (actually gitk can be called from git-gui)
> this is the wrong approach.
> use branches to reference the different ressources (rtl, simulation, layout).
> then track these branches between them for deliveries and work/flow.
>
> use tags to mark specific releases/cuts.
> you can create an alias: git-show-branch | tail -r
>   
>
> yes, I used to be scared by sha1 too: I even created numbered tags for
> each commit. Until I read more about git, and stopped expecting using
> git as svn/cvs.
>   
> no, it would kill the right approach: embrace the index, and never look back.
>   
>
> you have to adapt your methods instead: trust another ASIC designer :-)
>   
Previous: Christian MICHONNext: Jakub Narebski
Message 9 of 11 in “Verilog/ASIC development support is insufficient in git , help!”
  1. Justin LeungMay 11, 2008
  2. Kevin BallardMay 11, 2008
  3. Justin LeungMay 11, 2008
  4. Kevin BallardMay 11, 2008
  5. Justin LeungMay 12, 2008
  6. Dana HowMay 12, 2008
  7. Justin LeungMay 12, 2008
  8. Christian MICHONMay 11, 2008
  9. Justin LeungMay 12, 2008
  10. Jakub NarebskiMay 11, 2008
  11. Daniel BarkalowMay 12, 2008

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