Re: Verilog/ASIC development support is insufficient in git , help!

From: Justin Leung <jleung@redback.com>
Date: May 11, 2008, 05:29 UTC
Message-ID: <83EE186A7AF140179C6C73B367471EC7@justinuTop>
In-Reply-To: <B03D1DC3-7088-41AF-BB8B-9A696E7C5B8E@sb.org>

Hi Kevin,

The ability of inter-user (designer-verifier) code sync'ing without letting the incomplete or incompatible RTL code to propagate to the main build stream is going to facilitate the design flow and efficiency .

The ability of local revision control means that no more over writing of design files until commit .

I think these 2 things will really buy us alot .

 Justin

Show 16 quoted lines

> Honestly, it sounds like SVN is actually a good fit here. Just because 
> git is awesome for many things does not mean it is the end-all-be-all  of 
> version control systems. SVN still has its place as the last true 
> centralized system. Given your constraints and workflow, why do you  think 
> git is better than SVN?
>
> -Kevin Ballard
>
> -- 
> Kevin Ballard
> http://kevin.sb.org
> kevin@sb.org
> http://www.tildesoft.com
>
>
>