Re: [PATCH v2] Makefile: collect some Makefile variables instead of directly assignment
- From
Junio C Hamano <gitster@pobox.com>
- Date
- Jan 21, 2015, 09:23 UTC
- Message-ID
- <xmqqzj9cwkq4.fsf@gitster.dls.corp.google.com>
- In-Reply-To
- <1421830161-27623-1-git-send-email-kuleshovmail@gmail.com>
Alexander Kuleshov <kuleshovmail@gmail.com> writes:
> Some of Makefile variables as TEST_PROGRAMS_NEED_X and BUILTIN_OBJS filled > directly by hand, let's collect it with the standard functions of 'make' util.
I am not sure if we want to do this.
$(wildcard) is a double-edged sword. It will grab any file that matches on the filesystem, not just the ones we want to include in the Git source set. I often have a file called test-something and I'd prefer not to see such a random thing included in the build, only because the filename matches some pattern.
While "we consider anything with a name that match the pattern we say matter (e.g. test-*.c or builtin/*.c) as part of the source set" is sometimes handy (it allows us to be lazy), it risks surprising unsuspecting users.
So I dunno.