Re: Revised PPC assembly implementation

From: linux@horizon.com <linux@horizon.com>
Date: Apr 26, 2005, 02:08 UTC
Message-ID: <20050426021455.21115.qmail@science.horizon.com>
In-Reply-To: <20050425161746.7d943e62.davem@davemloft.net>

>From davem@davemloft.net Mon Apr 25 23:26:06 2005

Date: Mon, 25 Apr 2005 16:17:46 -0700
From: "David S. Miller" <davem@davemloft.net>
To: Paul Mackerras <paulus@samba.org>
Cc: linux@horizon.com, git@vger.kernel.org
Subject: Re: Revised PPC assembly implementation
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On Tue, 26 Apr 2005 09:00:45 +1000 Paul Mackerras <paulus@samba.org> wrote:

Show 5 quoted lines

> The main loop seems to be taking about 560 cycles (assuming that
> essentially all the time spent in my little test program is spent in
> the main loop).  It contains about 1000 integer instructions, which
> will take at least 500 cycles, as we have 2 ALUs.  So we are already
> within about 10% of the theoretical optimum.

Time to bust out the altivec perhaps :)

Do a block with the integer ALUs in parallel with a block done using Altivec :-) There should be enough spare insn slots so that the loads are absorbed properly.

Unlike UltraSPARC's VIS, with altivec you can reasonably do shifts and rotates, which is the only reason I'm suggesting this.