Re: Unaligned accesses in sha1dc

From: Junio C Hamano <gitster@pobox.com>
Date: Jun 1, 2017, 09:53 UTC
Message-ID: <xmqqwp8w3uff.fsf@gitster.mtv.corp.google.com>
In-Reply-To: <5100A096-EBAC-4B01-A94D-69D31093148D@gmail.com>

Lars Schneider <larsxschneider@gmail.com> writes:

Show 13 quoted lines

>> On 01 Jun 2017, at 10:28, Andreas Schwab <schwab@suse.de> wrote:
>> 
>> The sh1dc implementation is making unaligned accesses, which will crash
>> on some architectures, others have to emulate them in software.
>
> Is SPARC an architecture that would run into this problem? I think
> there was a thread a few days ago about this...
>
> What architectures are affected by this? I think I read somewhere
> that ARM requires aligned accesses, too, right?
>
> I wonder if it makes sense to emulate SPARC/ARM/... with QEMU on TravisCI [1].
> Is this what you had in mind with "emulate" or do you see a better way?

I think Andreas's "emulate" is that on these architectures often the kernel catches the hardware trap and makes the unaligned access appear to "just work" to the userland software, just like in very old days, i386 and i486 without 387/487 used software floating point "emulation" to give illusion to the userland softare that the co processor was available.

Having to trap and emulate of course costs cycles, and if the userland is written in such a way not to do an unaligned access in the first place.

Depending on the model of "ARM" (or "SPARC") emulated with QEMU, and depending on the OS that runs on such an "ARM" or "SPARC", we may not see this---if the emulated OS has the "software unaligned-access emulation" our userland may not see a SIGBUS.