From: Kevin Ballard <kevin@sb.org>
Date: Sun, 11 May 2008 05:21:32 GMT
Subject: Re: Verilog/ASIC development support is insufficient in git , help!
Message-ID: <B03D1DC3-7088-41AF-BB8B-9A696E7C5B8E@sb.org>
In-Reply-To: <BA7F9A3C7EDA4CDD99016093B0DB55C0@justinuTop>

On May 11, 2008, at 12:08 AM, Justin Leung wrote:

> Hi all,
>
> * This email probably represent the whole hardware ASIC community  
> about git *
>
> I'm evaluating Git as the replacement of CVS for the ASIC group in  
> my company,
> but things are moving along very bumpy.
>
> I (and many others doing the evaluation) love the tool dearly; we  
> love the local repository and inter-db sync'ing .
> I see a lot of potential in productivity and changes in work model  
> that helps efficiency in ASIC dev.
>
> BUT, my managers, some veterans, and directors are EXTREMELY  
> concerned about the ease-of-use..
> so much that they are going to pick SVN !  uh-oh....i m serious =(
>
> Alot of people argued, why not SVN ? it's CVS++ and it's ease of use  
> not a problem when comparing to Git.
>
> here are the things not fitting right in ASIC dev:
>
> - no incremental revision numbers (they are so scared of the 40hex  
> SHA1)
>
> - Inability to reference without SHA1, they want simple numbering  
> (ie, version 100, 120, 120.1, 130.4.5)
>
> - Inability to refer to a file by a simple number
> (the backend guys will be confused by SHA1; they can't work with  
> anything more than 4-5 digits)
>
> - Complexity of commands (although we can have warpper, but real git  
> commands for non-sw guys is not going to happen)
>
> Most hardware chip designers were using CVS since their first job.
> It suited the purpose very well.
>
> Most RTL design veterans only use less then 5-6 cvs commands in  
> their whole life (LOL, i m serious) :
>
> $ cvs checkout
> $ cvs update
> $ cvs log
> $ cvs diff (tkdiff)
> $ cvs status
> $ cvs commit
>
> We don't use branches.
> Our model is strict forward with a centralized, one main branch  
> model to avoid mistakes .
> We see branches as evil ; some merges in Verilog codes means another  
> 10+ hours of simulation and regression.
>
> [snip]

Honestly, it sounds like SVN is actually a good fit here. Just because  
git is awesome for many things does not mean it is the end-all-be-all  
of version control systems. SVN still has its place as the last true  
centralized system. Given your constraints and workflow, why do you  
think git is better than SVN?

-Kevin Ballard

-- 
Kevin Ballard
http://kevin.sb.org
kevin@sb.org
http://www.tildesoft.com