{"thread":{"id":"8662","subject":"git-send-email (Fw: Delivery reports about your email [FAILED(1)])","startedAt":"2007-06-20T10:42:02Z","lastAt":"2010-09-07T16:12:13Z","messageCount":2,"participants":["David Miller","Ryan Anderson"],"isPatch":false,"patchVersion":null,"patchTotal":null},"messages":[{"id":"45429","messageId":"20070620.034202.35337858.davem@davemloft.net","threadId":"8662","inReplyTo":null,"subject":"git-send-email (Fw: Delivery reports about your email [FAILED(1)])","fromName":"David Miller","fromEmail":"davem@davemloft.net","sentAt":"2007-06-20T10:42:02Z","receivedAt":"2007-06-20T10:42:02Z","isPatch":false,"sender":{"key":"davem@davemloft.net","avatar":null},"body":"\nLooks like at least some mailers don't like the Message-Id's\nbeing spit out by the version of git-send-email this person\nis using.\n\nJust FYI from your friendly vger postmaster. :-)\n\n\nThis is a collection of reports about email delivery\nprocess concerning a message you originated.\n\nSome explanations/translations for these reports\ncan be found at:\n http://www.zmailer.org/delivery-report-decoding.html\n\nGeneric VGER note: Joining/leaving VGER's lists thru server:\n\t\t\tmajordomo@vger.kernel.org\n\nReporting-MTA: dns; vger.kernel.org\nReturn-Path: \nArrival-Date: Wed, 20 Jun 2007 06:36:19 -0400\nLocal-Spool-ID: S1763440AbXFTKgT\n\n\nFAILED:\n Original Recipient:\n rfc822;jan.kromel@lynx.sk\n Final Recipient:\n RFC822;jan.kromel@lynx.sk\n Status:\n 5.0.0\n Remote MTA:\n dns; ke.lynx.sk (85.159.105.18|25|209.132.176.167|35055)\n Last Attempt Date:\n Wed, 20 Jun 2007 06:36:35 -0400\n X-ZTAID:\n smtp[23596]\n Diagnostic Code:\n smtp; 553 (Message-Id header line format error)\n Control data:\n smtp lynx.sk jan.kromel@lynx.sk 99\n Diagnostic texts:\n <<- MAIL From: BODY=8BITMIME SIZE=23117\n ->> 250 2.1.0 ... Sender ok\n <<- RCPT To: NOTIFY=FAILURE ORCPT=rfc822;jan.kromel@lynx.sk\n ->> 250 2.1.5 ... Recipient ok\n <<- DATA\n ->> 354 Enter mail, end with \".\" on a line by itself\n <<- .\n ->> 553 5.0.0 Message-Id header line format error\n\nFollowing is a copy of MESSAGE/DELIVERY-STATUS format section below.\nIt is copied here in case your email client is unable to show it to you.\nThe information here below is in Internet Standard format designed to\nassist automatic, and accurate presentation and usage of said information.\nIn case you need human assistance from the Postmaster(s) of the system which\nsent you this report, please include this information in your question!\n\n Virtually Yours,\n Automatic Email Delivery Software\n\nReporting-MTA: dns; vger.kernel.org\nArrival-Date: Wed, 20 Jun 2007 06:36:19 -0400\nLocal-Spool-ID: S1763440AbXFTKgT\n\nOriginal-Recipient: rfc822;jan.kromel@lynx.sk\nFinal-Recipient: RFC822;jan.kromel@lynx.sk\nAction: failed\nStatus: 5.0.0\nRemote-MTA: dns; ke.lynx.sk (85.159.105.18|25|209.132.176.167|35055)\nLast-Attempt-Date: Wed, 20 Jun 2007 06:36:35 -0400\nDiagnostic-Code: smtp; 553 (Message-Id header line format error)\n\n\nFollowing is copy of the message headers. Original message content may\nbe in subsequent parts of this MESSAGE/DELIVERY-STATUS structure.\n\nReceived: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1763440AbXFTKgT; Wed, 20 Jun 2007 06:36:19 -0400\nReceived: (majordomo@vger.kernel.org) by vger.kernel.org id S1761052AbXFTKfu\n\t(ORCPT );\n\tWed, 20 Jun 2007 06:35:50 -0400\nReceived: from mail.gmx.net ([213.165.64.20]:40751 \"HELO mail.gmx.net\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP\n\tid S1758129AbXFTKft (ORCPT );\n\tWed, 20 Jun 2007 06:35:49 -0400\nReceived: (qmail invoked by alias); 20 Jun 2007 10:35:45 -0000\nReceived: from i577B9F78.versanet.de (EHLO localhost) [87.123.159.120]\n by mail.gmx.net (mp052) with SMTP; 20 Jun 2007 12:35:45 +0200\nX-Authenticated: #5039886\nX-Provags-ID: V01U2FsdGVkX19FuG9DlANFUAB1y6743T/D78UN2sHlxVX5/236jp\n\tMRleI9FWyt5fy+\nFrom:\t=?utf-8?q?Bj=C3=B6rn=20Steinbrink?= \nTo:\teranian@hpl.hp.com\nCc:\toprofile-list@lists.sourceforge.net, wcohen@redhat.com, ak@suse.de,\n\tperfmon@napali.hpl.hp.com, linux-kernel@vger.kernel.org,\n\tlevon@movementarian.org, akpm@linux-foundation.org, mingo@elte.hu,\n\t=?utf-8?q?Bj=C3=B6rn=20Steinbrink?= \nSubject: [PATCH 2/2] Finish separation of the performance counter allocator from the NMI watchdog\nDate:\tWed, 20 Jun 2007 12:35:57 +0200\nMessage-Id: <11823357623688-git-send-email->\nX-Mailer: git-send-email 1.5.2.2\nIn-Reply-To: <11823357591180-git-send-email->\nReferences: <20070618103214.GA12045@atjola.homenet>\n <11823357571842-git-send-email->\n <11823357591180-git-send-email->\nMIME-Version: 1.0\nContent-Type: text/plain; charset=utf-8\nContent-Transfer-Encoding: 8bit\nX-Y-GMX-Trusted: 0\nSender:\tlinux-kernel-owner@vger.kernel.org\nPrecedence: bulk\nX-Mailing-List:\tlinux-kernel@vger.kernel.org\n\n\n\n\n\n\n\nReceived: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand=\n\n\tid S1763440AbXFTKgT; Wed, 20 Jun 2007 06:36:19 -0400\nReceived: (majordomo@vger.kernel.org) by vger.kernel.org id S1761052AbX=\nFTKfu\n\t(ORCPT );\n\tWed, 20 Jun 2007 06:35:50 -0400\nReceived: from mail.gmx.net ([213.165.64.20]:40751 \"HELO mail.gmx.net\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP\n\tid S1758129AbXFTKft (ORCPT );\n\tWed, 20 Jun 2007 06:35:49 -0400\nReceived: (qmail invoked by alias); 20 Jun 2007 10:35:45 -0000\nReceived: from i577B9F78.versanet.de (EHLO localhost) [87.123.159.120]\n by mail.gmx.net (mp052) with SMTP; 20 Jun 2007 12:35:45 +0200\nX-Authenticated: #5039886\nX-Provags-ID: V01U2FsdGVkX19FuG9DlANFUAB1y6743T/D78UN2sHlxVX5/236jp\n\tMRleI9FWyt5fy+\nFrom:\t=3D?utf-8?q?Bj=3DC3=3DB6rn=3D20Steinbrink?=3D \nTo:\teranian@hpl.hp.com\nCc:\toprofile-list@lists.sourceforge.net, wcohen@redhat.com, ak@suse.de,=\n\n\tperfmon@napali.hpl.hp.com, linux-kernel@vger.kernel.org,\n\tlevon@movementarian.org, akpm@linux-foundation.org, mingo@elte.hu,\n\t=3D?utf-8?q?Bj=3DC3=3DB6rn=3D20Steinbrink?=3D \nSubject: [PATCH 2/2] Finish separation of the performance counter alloc=\nator from the NMI watchdog\nDate:\tWed, 20 Jun 2007 12:35:57 +0200\nMessage-Id: <11823357623688-git-send-email->\nX-Mailer: git-send-email 1.5.2.2\nIn-Reply-To: <11823357591180-git-send-email->\nReferences: <20070618103214.GA12045@atjola.homenet>\n <11823357571842-git-send-email->\n <11823357591180-git-send-email->\nMIME-Version: 1.0\nContent-Type: text/plain; charset=3Dutf-8\nContent-Transfer-Encoding: 8bit\nX-Y-GMX-Trusted: 0\nSender:\tlinux-kernel-owner@vger.kernel.org\nPrecedence: bulk\nX-Mailing-List:\tlinux-kernel@vger.kernel.org\n\nFrom: Bj=C3=B6rn Steinbrink \n\nRemove the nmi part from all names in the performance counter allocator=\n\nand move all declarations into their own header file.\n\nSigned-off-by: Bj=C3=B6rn Steinbrink \n---\n arch/i386/kernel/apic.c | 1 +\n arch/i386/kernel/cpu/perfctr-watchdog.c | 27 +++++++-------\n arch/i386/kernel/cpu/perfctr.c | 58 +++++++++++++++--------=\n-------\n arch/i386/oprofile/nmi_int.c | 4 +-\n arch/i386/oprofile/op_model_athlon.c | 10 +++---\n arch/i386/oprofile/op_model_p4.c | 28 +++++++-------\n arch/i386/oprofile/op_model_ppro.c | 10 +++---\n arch/x86_64/kernel/apic.c | 1 +\n arch/x86_64/kernel/time.c | 12 +++---\n include/asm-i386/nmi.h | 7 ----\n include/asm-i386/perfctr.h | 15 ++++++++\n include/asm-x86_64/nmi.h | 7 ----\n include/asm-x86_64/perfctr.h | 15 ++++++++\n 13 files changed, 107 insertions(+), 88 deletions(-)\n create mode 100644 include/asm-i386/perfctr.h\n create mode 100644 include/asm-x86_64/perfctr.h\n\ndiff --git a/arch/i386/kernel/apic.c b/arch/i386/kernel/apic.c\nindex 88b74e3..16a5140 100644\n--- a/arch/i386/kernel/apic.c\n+++ b/arch/i386/kernel/apic.c\n@@ -38,6 +38,7 @@\n #include \n #include \n #include \n+#include \n =\n\n #include \n #include \ndiff --git a/arch/i386/kernel/cpu/perfctr-watchdog.c b/arch/i386/kernel=\n/cpu/perfctr-watchdog.c\nindex 2ae39eb..d8fabd2 100644\n--- a/arch/i386/kernel/cpu/perfctr-watchdog.c\n+++ b/arch/i386/kernel/cpu/perfctr-watchdog.c\n@@ -13,6 +13,7 @@\n #include \n #include \n #include \n+#include \n =\n\n struct nmi_watchdog_ctlblk {\n \tunsigned int cccr_msr;\n@@ -165,11 +166,11 @@ static void single_msr_stop_watchdog(void)\n =\n\n static int single_msr_reserve(void)\n {\n-\tif (!reserve_perfctr_nmi(wd_ops->perfctr))\n+\tif (!reserve_perfctr(wd_ops->perfctr))\n \t\treturn 0;\n =\n\n-\tif (!reserve_evntsel_nmi(wd_ops->evntsel)) {\n-\t\trelease_perfctr_nmi(wd_ops->perfctr);\n+\tif (!reserve_evntsel(wd_ops->evntsel)) {\n+\t\trelease_perfctr(wd_ops->perfctr);\n \t\treturn 0;\n \t}\n \treturn 1;\n@@ -177,8 +178,8 @@ static int single_msr_reserve(void)\n =\n\n static void single_msr_unreserve(void)\n {\n-\trelease_evntsel_nmi(wd_ops->evntsel);\n-\trelease_perfctr_nmi(wd_ops->perfctr);\n+\trelease_evntsel(wd_ops->evntsel);\n+\trelease_perfctr(wd_ops->perfctr);\n }\n =\n\n static void single_msr_rearm(struct nmi_watchdog_ctlblk *wd, unsigned =\nnmi_hz)\n@@ -352,23 +353,23 @@ static void stop_p4_watchdog(void)\n =\n\n static int p4_reserve(void)\n {\n-\tif (!reserve_perfctr_nmi(MSR_P4_IQ_PERFCTR0))\n+\tif (!reserve_perfctr(MSR_P4_IQ_PERFCTR0))\n \t\treturn 0;\n #ifdef CONFIG_SMP\n-\tif (smp_num_siblings > 1 && !reserve_perfctr_nmi(MSR_P4_IQ_PERFCTR1))=\n\n+\tif (smp_num_siblings > 1 && !reserve_perfctr(MSR_P4_IQ_PERFCTR1))\n \t\tgoto fail1;\n #endif\n-\tif (!reserve_evntsel_nmi(MSR_P4_CRU_ESCR0))\n+\tif (!reserve_evntsel(MSR_P4_CRU_ESCR0))\n \t\tgoto fail2;\n \t/* RED-PEN why is ESCR1 not reserved here? */\n \treturn 1;\n fail2:\n #ifdef CONFIG_SMP\n \tif (smp_num_siblings > 1)\n-\t\trelease_perfctr_nmi(MSR_P4_IQ_PERFCTR1);\n+\t\trelease_perfctr(MSR_P4_IQ_PERFCTR1);\n fail1:\n #endif\n-\trelease_perfctr_nmi(MSR_P4_IQ_PERFCTR0);\n+\trelease_perfctr(MSR_P4_IQ_PERFCTR0);\n \treturn 0;\n }\n =\n\n@@ -376,10 +377,10 @@ static void p4_unreserve(void)\n {\n #ifdef CONFIG_SMP\n \tif (smp_num_siblings > 1)\n-\t\trelease_perfctr_nmi(MSR_P4_IQ_PERFCTR1);\n+\t\trelease_perfctr(MSR_P4_IQ_PERFCTR1);\n #endif\n-\trelease_evntsel_nmi(MSR_P4_CRU_ESCR0);\n-\trelease_perfctr_nmi(MSR_P4_IQ_PERFCTR0);\n+\trelease_evntsel(MSR_P4_CRU_ESCR0);\n+\trelease_perfctr(MSR_P4_IQ_PERFCTR0);\n }\n =\n\n static void p4_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)\ndiff --git a/arch/i386/kernel/cpu/perfctr.c b/arch/i386/kernel/cpu/perf=\nctr.c\nindex fece4fc..cbf57ce 100644\n--- a/arch/i386/kernel/cpu/perfctr.c\n+++ b/arch/i386/kernel/cpu/perfctr.c\n@@ -35,14 +35,14 @@ static struct perfctr_base_regs arch_perfmon_base_r=\negs =3D {\n */\n #define NMI_MAX_COUNTER_BITS 66\n =\n\n-/* perfctr_nmi_owner tracks the ownership of the perfctr registers:\n- * evtsel_nmi_owner tracks the ownership of the event selection\n+/* perfctr_owner tracks the ownership of the perfctr registers:\n+ * evtsel_owner tracks the ownership of the event selection\n * - different performance counters/ event selection may be reserved f=\nor\n * different subsystems this reservation system just tries to coordi=\nnate\n * things a little\n */\n-static DECLARE_BITMAP(perfctr_nmi_owner, NMI_MAX_COUNTER_BITS);\n-static DECLARE_BITMAP(evntsel_nmi_owner, NMI_MAX_COUNTER_BITS);\n+static DECLARE_BITMAP(perfctr_owner, NMI_MAX_COUNTER_BITS);\n+static DECLARE_BITMAP(evntsel_owner, NMI_MAX_COUNTER_BITS);\n =\n\n void __devinit probe_performance_counters(void)\n {\n@@ -77,102 +77,102 @@ void __devinit probe_performance_counters(void)\n }\n =\n\n /* converts an msr to an appropriate reservation bit */\n-static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)\n+static inline unsigned int perfctr_msr_to_bit(unsigned int msr)\n {\n \treturn msr - perfctr_base_regs->perfctr;\n }\n =\n\n /* converts an msr to an appropriate reservation bit */\n /* returns the bit offset of the event selection register */\n-static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)\n+static inline unsigned int evntsel_msr_to_bit(unsigned int msr)\n {\n \treturn msr - perfctr_base_regs->evntsel;\n }\n =\n\n /* checks for a bit availability (hack for oprofile) */\n-int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)\n+int avail_to_resrv_perfctr_bit(unsigned int counter)\n {\n \tif (!perfctr_base_regs)\n \t\treturn 0;\n =\n\n \tBUG_ON(counter > NMI_MAX_COUNTER_BITS);\n =\n\n-\treturn (!test_bit(counter, perfctr_nmi_owner));\n+\treturn (!test_bit(counter, perfctr_owner));\n }\n =\n\n /* checks the an msr for availability */\n-int avail_to_resrv_perfctr_nmi(unsigned int msr)\n+int avail_to_resrv_perfctr(unsigned int msr)\n {\n \tunsigned int counter;\n =\n\n \tif (!perfctr_base_regs)\n \t\treturn 0;\n =\n\n-\tcounter =3D nmi_perfctr_msr_to_bit(msr);\n+\tcounter =3D perfctr_msr_to_bit(msr);\n \tBUG_ON(counter > NMI_MAX_COUNTER_BITS);\n =\n\n-\treturn (!test_bit(counter, perfctr_nmi_owner));\n+\treturn (!test_bit(counter, perfctr_owner));\n }\n =\n\n-int reserve_perfctr_nmi(unsigned int msr)\n+int reserve_perfctr(unsigned int msr)\n {\n \tunsigned int counter;\n =\n\n \tif (!perfctr_base_regs)\n \t\treturn 0;\n =\n\n-\tcounter =3D nmi_perfctr_msr_to_bit(msr);\n+\tcounter =3D perfctr_msr_to_bit(msr);\n \tBUG_ON(counter > NMI_MAX_COUNTER_BITS);\n =\n\n-\tif (!test_and_set_bit(counter, perfctr_nmi_owner))\n+\tif (!test_and_set_bit(counter, perfctr_owner))\n \t\treturn 1;\n \treturn 0;\n }\n =\n\n-void release_perfctr_nmi(unsigned int msr)\n+void release_perfctr(unsigned int msr)\n {\n \tunsigned int counter;\n =\n\n \tif (!perfctr_base_regs)\n \t\treturn;\n =\n\n-\tcounter =3D nmi_perfctr_msr_to_bit(msr);\n+\tcounter =3D perfctr_msr_to_bit(msr);\n \tBUG_ON(counter > NMI_MAX_COUNTER_BITS);\n =\n\n-\tclear_bit(counter, perfctr_nmi_owner);\n+\tclear_bit(counter, perfctr_owner);\n }\n =\n\n-int reserve_evntsel_nmi(unsigned int msr)\n+int reserve_evntsel(unsigned int msr)\n {\n \tunsigned int counter;\n =\n\n \tif (!perfctr_base_regs)\n \t\treturn 0;\n =\n\n-\tcounter =3D nmi_evntsel_msr_to_bit(msr);\n+\tcounter =3D evntsel_msr_to_bit(msr);\n \tBUG_ON(counter > NMI_MAX_COUNTER_BITS);\n =\n\n-\tif (!test_and_set_bit(counter, evntsel_nmi_owner))\n+\tif (!test_and_set_bit(counter, evntsel_owner))\n \t\treturn 1;\n \treturn 0;\n }\n =\n\n-void release_evntsel_nmi(unsigned int msr)\n+void release_evntsel(unsigned int msr)\n {\n \tunsigned int counter;\n =\n\n \tif (!perfctr_base_regs)\n \t\treturn;\n =\n\n-\tcounter =3D nmi_evntsel_msr_to_bit(msr);\n+\tcounter =3D evntsel_msr_to_bit(msr);\n \tBUG_ON(counter > NMI_MAX_COUNTER_BITS);\n =\n\n-\tclear_bit(counter, evntsel_nmi_owner);\n+\tclear_bit(counter, evntsel_owner);\n }\n =\n\n-EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);\n-EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);\n-EXPORT_SYMBOL(reserve_perfctr_nmi);\n-EXPORT_SYMBOL(release_perfctr_nmi);\n-EXPORT_SYMBOL(reserve_evntsel_nmi);\n-EXPORT_SYMBOL(release_evntsel_nmi);\n+EXPORT_SYMBOL(avail_to_resrv_perfctr);\n+EXPORT_SYMBOL(avail_to_resrv_perfctr_bit);\n+EXPORT_SYMBOL(reserve_perfctr);\n+EXPORT_SYMBOL(release_perfctr);\n+EXPORT_SYMBOL(reserve_evntsel);\n+EXPORT_SYMBOL(release_evntsel);\ndiff --git a/arch/i386/oprofile/nmi_int.c b/arch/i386/oprofile/nmi_int.=\nc\nindex 11b7a51..b00ae99 100644\n--- a/arch/i386/oprofile/nmi_int.c\n+++ b/arch/i386/oprofile/nmi_int.c\n@@ -15,7 +15,7 @@\n #include \n #include \n #include \n-#include \n+#include \n #include \n #include \n =\n\n@@ -324,7 +324,7 @@ static int nmi_create_files(struct super_block * sb=\n, struct dentry * root)\n \t\t * NOTE: assumes 1:1 mapping here (that counters are organized\n \t\t * sequentially in their struct assignment).\n \t\t */\n-\t\tif (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))\n+\t\tif (unlikely(!avail_to_resrv_perfctr_bit(i)))\n \t\t\tcontinue;\n =\n\n \t\tsnprintf(buf, sizeof(buf), \"%d\", i);\ndiff --git a/arch/i386/oprofile/op_model_athlon.c b/arch/i386/oprofile/=\nop_model_athlon.c\nindex 3057a19..b1e9902 100644\n--- a/arch/i386/oprofile/op_model_athlon.c\n+++ b/arch/i386/oprofile/op_model_athlon.c\n@@ -13,7 +13,7 @@\n #include \n #include \n #include \n-#include \n+#include \n =\n\n #include \"op_x86_model.h\"\n #include \"op_counter.h\"\n@@ -45,14 +45,14 @@ static void athlon_fill_in_addresses(struct op_msrs=\n * const msrs)\n \tint i;\n =\n\n \tfor (i=3D0; i < NUM_COUNTERS; i++) {\n-\t\tif (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))\n+\t\tif (reserve_perfctr(MSR_K7_PERFCTR0 + i))\n \t\t\tmsrs->counters[i].addr =3D MSR_K7_PERFCTR0 + i;\n \t\telse\n \t\t\tmsrs->counters[i].addr =3D 0;\n \t}\n =\n\n \tfor (i=3D0; i < NUM_CONTROLS; i++) {\n-\t\tif (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))\n+\t\tif (reserve_evntsel(MSR_K7_EVNTSEL0 + i))\n \t\t\tmsrs->controls[i].addr =3D MSR_K7_EVNTSEL0 + i;\n \t\telse\n \t\t\tmsrs->controls[i].addr =3D 0;\n@@ -160,11 +160,11 @@ static void athlon_shutdown(struct op_msrs const =\n* const msrs)\n =\n\n \tfor (i =3D 0 ; i < NUM_COUNTERS ; ++i) {\n \t\tif (CTR_IS_RESERVED(msrs,i))\n-\t\t\trelease_perfctr_nmi(MSR_K7_PERFCTR0 + i);\n+\t\t\trelease_perfctr(MSR_K7_PERFCTR0 + i);\n \t}\n \tfor (i =3D 0 ; i < NUM_CONTROLS ; ++i) {\n \t\tif (CTRL_IS_RESERVED(msrs,i))\n-\t\t\trelease_evntsel_nmi(MSR_K7_EVNTSEL0 + i);\n+\t\t\trelease_evntsel(MSR_K7_EVNTSEL0 + i);\n \t}\n }\n =\n\ndiff --git a/arch/i386/oprofile/op_model_p4.c b/arch/i386/oprofile/op_m=\nodel_p4.c\nindex 4792592..6ba5856 100644\n--- a/arch/i386/oprofile/op_model_p4.c\n+++ b/arch/i386/oprofile/op_model_p4.c\n@@ -14,7 +14,7 @@\n #include \n #include \n #include \n-#include \n+#include \n =\n\n #include \"op_x86_model.h\"\n #include \"op_counter.h\"\n@@ -413,7 +413,7 @@ static void p4_fill_in_addresses(struct op_msrs * c=\nonst msrs)\n \tfor (i =3D 0; i < num_counters; ++i) {\n \t\taddr =3D p4_counters[VIRT_CTR(stag, i)].counter_address;\n \t\tcccraddr =3D p4_counters[VIRT_CTR(stag, i)].cccr_address;\n-\t\tif (reserve_perfctr_nmi(addr)){\n+\t\tif (reserve_perfctr(addr)){\n \t\t\tmsrs->counters[i].addr =3D addr;\n \t\t\tmsrs->controls[i].addr =3D cccraddr;\n \t\t}\n@@ -422,7 +422,7 @@ static void p4_fill_in_addresses(struct op_msrs * c=\nonst msrs)\n \t/* 43 ESCR registers in three or four discontiguous group */\n \tfor (addr =3D MSR_P4_BSU_ESCR0 + stag;\n \t addr < MSR_P4_IQ_ESCR0; ++i, addr +=3D addr_increment()) {\n-\t\tif (reserve_evntsel_nmi(addr))\n+\t\tif (reserve_evntsel(addr))\n \t\t\tmsrs->controls[i].addr =3D addr;\n \t}\n =\n\n@@ -431,32 +431,32 @@ static void p4_fill_in_addresses(struct op_msrs *=\n const msrs)\n \tif (boot_cpu_data.x86_model >=3D 0x3) {\n \t\tfor (addr =3D MSR_P4_BSU_ESCR0 + stag;\n \t\t addr <=3D MSR_P4_BSU_ESCR1; ++i, addr +=3D addr_increment()) {\n-\t\t\tif (reserve_evntsel_nmi(addr))\n+\t\t\tif (reserve_evntsel(addr))\n \t\t\t\tmsrs->controls[i].addr =3D addr;\n \t\t}\n \t} else {\n \t\tfor (addr =3D MSR_P4_IQ_ESCR0 + stag;\n \t\t addr <=3D MSR_P4_IQ_ESCR1; ++i, addr +=3D addr_increment()) {\n-\t\t\tif (reserve_evntsel_nmi(addr))\n+\t\t\tif (reserve_evntsel(addr))\n \t\t\t\tmsrs->controls[i].addr =3D addr;\n \t\t}\n \t}\n =\n\n \tfor (addr =3D MSR_P4_RAT_ESCR0 + stag;\n \t addr <=3D MSR_P4_SSU_ESCR0; ++i, addr +=3D addr_increment()) {\n-\t\tif (reserve_evntsel_nmi(addr))\n+\t\tif (reserve_evntsel(addr))\n \t\t\tmsrs->controls[i].addr =3D addr;\n \t}\n \t=\n\n \tfor (addr =3D MSR_P4_MS_ESCR0 + stag;\n \t addr <=3D MSR_P4_TC_ESCR1; ++i, addr +=3D addr_increment()) { =\n\n-\t\tif (reserve_evntsel_nmi(addr))\n+\t\tif (reserve_evntsel(addr))\n \t\t\tmsrs->controls[i].addr =3D addr;\n \t}\n \t=\n\n \tfor (addr =3D MSR_P4_IX_ESCR0 + stag;\n \t addr <=3D MSR_P4_CRU_ESCR3; ++i, addr +=3D addr_increment()) { =\n\n-\t\tif (reserve_evntsel_nmi(addr))\n+\t\tif (reserve_evntsel(addr))\n \t\t\tmsrs->controls[i].addr =3D addr;\n \t}\n =\n\n@@ -464,21 +464,21 @@ static void p4_fill_in_addresses(struct op_msrs *=\n const msrs)\n =\n\n \tif (num_counters =3D=3D NUM_COUNTERS_NON_HT) {\t\t=\n\n \t\t/* standard non-HT CPUs handle both remaining ESCRs*/\n-\t\tif (reserve_evntsel_nmi(MSR_P4_CRU_ESCR5))\n+\t\tif (reserve_evntsel(MSR_P4_CRU_ESCR5))\n \t\t\tmsrs->controls[i++].addr =3D MSR_P4_CRU_ESCR5;\n-\t\tif (reserve_evntsel_nmi(MSR_P4_CRU_ESCR4))\n+\t\tif (reserve_evntsel(MSR_P4_CRU_ESCR4))\n \t\t\tmsrs->controls[i++].addr =3D MSR_P4_CRU_ESCR4;\n =\n\n \t} else if (stag =3D=3D 0) {\n \t\t/* HT CPUs give the first remainder to the even thread, as\n \t\t the 32nd control register */\n-\t\tif (reserve_evntsel_nmi(MSR_P4_CRU_ESCR4))\n+\t\tif (reserve_evntsel(MSR_P4_CRU_ESCR4))\n \t\t\tmsrs->controls[i++].addr =3D MSR_P4_CRU_ESCR4;\n =\n\n \t} else {\n \t\t/* and two copies of the second to the odd thread,\n \t\t for the 22st and 23nd control registers */\n-\t\tif (reserve_evntsel_nmi(MSR_P4_CRU_ESCR5)) {\n+\t\tif (reserve_evntsel(MSR_P4_CRU_ESCR5)) {\n \t\t\tmsrs->controls[i++].addr =3D MSR_P4_CRU_ESCR5;\n \t\t\tmsrs->controls[i++].addr =3D MSR_P4_CRU_ESCR5;\n \t\t}\n@@ -684,7 +684,7 @@ static void p4_shutdown(struct op_msrs const * cons=\nt msrs)\n =\n\n \tfor (i =3D 0 ; i < num_counters ; ++i) {\n \t\tif (CTR_IS_RESERVED(msrs,i))\n-\t\t\trelease_perfctr_nmi(msrs->counters[i].addr);\n+\t\t\trelease_perfctr(msrs->counters[i].addr);\n \t}\n \t/* some of the control registers are specially reserved in\n \t * conjunction with the counter registers (hence the starting offset)=\n.=\n\n@@ -692,7 +692,7 @@ static void p4_shutdown(struct op_msrs const * cons=\nt msrs)\n \t */\n \tfor (i =3D num_counters ; i < num_controls ; ++i) {\n \t\tif (CTRL_IS_RESERVED(msrs,i))\n-\t\t\trelease_evntsel_nmi(msrs->controls[i].addr);\n+\t\t\trelease_evntsel(msrs->controls[i].addr);\n \t}\n }\n =\n\ndiff --git a/arch/i386/oprofile/op_model_ppro.c b/arch/i386/oprofile/op=\n_model_ppro.c\nindex c554f52..5dfd93a 100644\n--- a/arch/i386/oprofile/op_model_ppro.c\n+++ b/arch/i386/oprofile/op_model_ppro.c\n@@ -14,7 +14,7 @@\n #include \n #include \n #include \n-#include \n+#include \n =\n\n #include \"op_x86_model.h\"\n #include \"op_counter.h\"\n@@ -47,14 +47,14 @@ static void ppro_fill_in_addresses(struct op_msrs *=\n const msrs)\n \tint i;\n =\n\n \tfor (i=3D0; i < NUM_COUNTERS; i++) {\n-\t\tif (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))\n+\t\tif (reserve_perfctr(MSR_P6_PERFCTR0 + i))\n \t\t\tmsrs->counters[i].addr =3D MSR_P6_PERFCTR0 + i;\n \t\telse\n \t\t\tmsrs->counters[i].addr =3D 0;\n \t}\n \t=\n\n \tfor (i=3D0; i < NUM_CONTROLS; i++) {\n-\t\tif (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))\n+\t\tif (reserve_evntsel(MSR_P6_EVNTSEL0 + i))\n \t\t\tmsrs->controls[i].addr =3D MSR_P6_EVNTSEL0 + i;\n \t\telse\n \t\t\tmsrs->controls[i].addr =3D 0;\n@@ -171,11 +171,11 @@ static void ppro_shutdown(struct op_msrs const * =\nconst msrs)\n =\n\n \tfor (i =3D 0 ; i < NUM_COUNTERS ; ++i) {\n \t\tif (CTR_IS_RESERVED(msrs,i))\n-\t\t\trelease_perfctr_nmi(MSR_P6_PERFCTR0 + i);\n+\t\t\trelease_perfctr(MSR_P6_PERFCTR0 + i);\n \t}\n \tfor (i =3D 0 ; i < NUM_CONTROLS ; ++i) {\n \t\tif (CTRL_IS_RESERVED(msrs,i))\n-\t\t\trelease_evntsel_nmi(MSR_P6_EVNTSEL0 + i);\n+\t\t\trelease_evntsel(MSR_P6_EVNTSEL0 + i);\n \t}\n }\n =\n\ndiff --git a/arch/x86_64/kernel/apic.c b/arch/x86_64/kernel/apic.c\nindex 892ebf8..c08cf0f 100644\n--- a/arch/x86_64/kernel/apic.c\n+++ b/arch/x86_64/kernel/apic.c\n@@ -33,6 +33,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \ndiff --git a/arch/x86_64/kernel/time.c b/arch/x86_64/kernel/time.c\nindex 4a0895b..d145547 100644\n--- a/arch/x86_64/kernel/time.c\n+++ b/arch/x86_64/kernel/time.c\n@@ -43,7 +43,7 @@\n #include \n #include \n #include \n-#include \n+#include \n =\n\n static char *timename =3D NULL;\n =\n\n@@ -261,7 +261,7 @@ static unsigned int __init tsc_calibrate_cpu_khz(vo=\nid)\n unsigned long flags;\n =\n\n for (i =3D 0; i < 4; i++)\n- if (avail_to_resrv_perfctr_nmi_bit(i))\n+ if (avail_to_resrv_perfctr_bit(i))\n break;\n no_ctr_free =3D (i =3D=3D 4);\n if (no_ctr_free) {\n@@ -270,8 +270,8 @@ static unsigned int __init tsc_calibrate_cpu_khz(vo=\nid)\n wrmsrl(MSR_K7_EVNTSEL3, 0);\n rdmsrl(MSR_K7_PERFCTR3, pmc3);\n } else {\n- reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i);\n- reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i);\n+ reserve_perfctr(MSR_K7_PERFCTR0 + i);\n+ reserve_evntsel(MSR_K7_EVNTSEL0 + i);\n }\n local_irq_save(flags);\n /* start meauring cycles, incrementing from 0 */\n@@ -289,8 +289,8 @@ static unsigned int __init tsc_calibrate_cpu_khz(vo=\nid)\n wrmsrl(MSR_K7_PERFCTR3, pmc3);\n wrmsrl(MSR_K7_EVNTSEL3, evntsel3);\n } else {\n- release_perfctr_nmi(MSR_K7_PERFCTR0 + i);\n- release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);\n+ release_perfctr(MSR_K7_PERFCTR0 + i);\n+ release_evntsel(MSR_K7_EVNTSEL0 + i);\n }\n =\n\n return pmc_now * tsc_khz / (tsc_now - tsc_start);\ndiff --git a/include/asm-i386/nmi.h b/include/asm-i386/nmi.h\nindex 736af6f..e189531 100644\n--- a/include/asm-i386/nmi.h\n+++ b/include/asm-i386/nmi.h\n@@ -18,13 +18,6 @@\n int do_nmi_callback(struct pt_regs *regs, int cpu);\n =\n\n extern int nmi_watchdog_enabled;\n-extern void probe_performance_counters(void);\n-extern int avail_to_resrv_perfctr_nmi_bit(unsigned int);\n-extern int avail_to_resrv_perfctr_nmi(unsigned int);\n-extern int reserve_perfctr_nmi(unsigned int);\n-extern void release_perfctr_nmi(unsigned int);\n-extern int reserve_evntsel_nmi(unsigned int);\n-extern void release_evntsel_nmi(unsigned int);\n =\n\n extern void setup_apic_nmi_watchdog (void *);\n extern void stop_apic_nmi_watchdog (void *);\ndiff --git a/include/asm-i386/perfctr.h b/include/asm-i386/perfctr.h\nnew file mode 100644\nindex 0000000..fbd4993\n--- /dev/null\n+++ b/include/asm-i386/perfctr.h\n@@ -0,0 +1,15 @@\n+/*\n+ * linux/include/asm-i386/perfctr.h\n+ */\n+#ifndef ASM_PERFCTR_H\n+#define ASM_PERFCTR_H\n+\n+extern void probe_performance_counters(void);\n+extern int avail_to_resrv_perfctr_bit(unsigned int);\n+extern int avail_to_resrv_perfctr(unsigned int);\n+extern int reserve_perfctr(unsigned int);\n+extern void release_perfctr(unsigned int);\n+extern int reserve_evntsel(unsigned int);\n+extern void release_evntsel(unsigned int);\n+\n+#endif /* ASM_PERFCTR_H */\ndiff --git a/include/asm-x86_64/nmi.h b/include/asm-x86_64/nmi.h\nindex d45fc62..666462c 100644\n--- a/include/asm-x86_64/nmi.h\n+++ b/include/asm-x86_64/nmi.h\n@@ -46,13 +46,6 @@ extern int unknown_nmi_panic;\n extern int nmi_watchdog_enabled;\n =\n\n extern int check_nmi_watchdog(void);\n-extern void probe_performance_counters(void);\n-extern int avail_to_resrv_perfctr_nmi_bit(unsigned int);\n-extern int avail_to_resrv_perfctr_nmi(unsigned int);\n-extern int reserve_perfctr_nmi(unsigned int);\n-extern void release_perfctr_nmi(unsigned int);\n-extern int reserve_evntsel_nmi(unsigned int);\n-extern void release_evntsel_nmi(unsigned int);\n =\n\n extern void setup_apic_nmi_watchdog (void *);\n extern void stop_apic_nmi_watchdog (void *);\ndiff --git a/include/asm-x86_64/perfctr.h b/include/asm-x86_64/perfctr.=\nh\nnew file mode 100644\nindex 0000000..9ff5c2d\n--- /dev/null\n+++ b/include/asm-x86_64/perfctr.h\n@@ -0,0 +1,15 @@\n+/*\n+ * linux/include/asm-x86_64/perfctr.h\n+ */\n+#ifndef ASM_PERFCTR_H\n+#define ASM_PERFCTR_H\n+\n+extern void probe_performance_counters(void);\n+extern int avail_to_resrv_perfctr_bit(unsigned int);\n+extern int avail_to_resrv_perfctr(unsigned int);\n+extern int reserve_perfctr(unsigned int);\n+extern void release_perfctr(unsigned int);\n+extern int reserve_evntsel(unsigned int);\n+extern void release_evntsel(unsigned int);\n+\n+#endif /* ASM_PERFCTR_H */\n-- =\n\n1.5.2.1\n\n-\nTo unsubscribe from this list: send the line \"unsubscribe linux-kernel\"=\n in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html\nPlease read the FAQ at http://www.tux.org/lkml/=\n"},{"id":"150215","messageId":"AANLkTin6LOUqJxuOhzHca9Hq52_a_GvFG2hqZs7WOtJO@mail.gmail.com","threadId":"8662","inReplyTo":"20070620.034202.35337858.davem@davemloft.net","subject":"Re: git-send-email (Fw: Delivery reports about your email [FAILED(1)])","fromName":"Ryan Anderson","fromEmail":"ryan@michonline.com","sentAt":"2010-09-07T16:12:13Z","receivedAt":"2010-09-07T16:12:13Z","isPatch":false,"sender":{"key":"ryan@michonline.com","avatar":null},"body":"On Wed, Jun 20, 2007 at 3:42 AM, David Miller wrote:\n>\n> Looks like at least some mailers don't like the Message-Id's\n> being spit out by the version of git-send-email this person\n> is using.\n\nI'm going to guess the problem is the lack of a \"@\" in the Message-Id:\n\n> Message-Id: <11823357623688-git-send-email->\n\nThat's not really right. :)\n\n> Just FYI from your friendly vger postmaster. :-)\n\nthanks.\n\n-- \nRyan\n"}]}