{"thread":{"id":"63110","subject":"[GSoC][Patch] Add more builtin patterns for userdiff: Add builtin patterns for Verilog","startedAt":"2025-03-13T14:23:10Z","lastAt":"2025-03-24T13:17:46Z","messageCount":2,"participants":["li li","Patrick Steinhardt"],"isPatch":true,"patchVersion":1,"patchTotal":null},"messages":[{"id":"514188","messageId":"SEZPR01MB5486F5B360F1DFA607C69F37A3D32@SEZPR01MB5486.apcprd01.prod.exchangelabs.com","threadId":"63110","inReplyTo":null,"subject":"[GSoC][Patch] Add more builtin patterns for userdiff: Add builtin patterns for Verilog","fromName":"li li","fromEmail":"li0371859@gmail.com","sentAt":"2025-03-13T14:23:05Z","receivedAt":"2025-03-13T14:23:10Z","isPatch":true,"sender":{"key":"li0371859@gmail.com","avatar":null},"body":"Add Verilog built-in to userdiff.c. I read the code and checked the previous mailing list. I found that if I want git to recognize Verilog syntax, I need to add Verilog regular expressions to the userdiff_driver array of userdiff.c and modify the .gitattributes file.\nYes, I did it.\nThe next step is to write test cases and submit patches.\nI am not sure if this is in line with the development process specifications. Maybe I should make some adjustments. If so, please let me know.\n\n\ndiff --git a/.gitattributes b/.gitattributes\nindex 43fa883a84..8aac8574f1 100644\n--- a/.gitattributes\n+++ b/.gitattributes\n@@ -6,6 +6,7 @@\n *.pm text eol=lf diff=perl\n *.py text eol=lf diff=python\n *.bat text eol=crlf\n+*.v text eof=lf diff=verilog\n CODE_OF_CONDUCT.md -whitespace\n /Documentation/**/*.adoc text eol=lf\n /command-list.txt text eol=lf\ndiff --git a/userdiff.c b/userdiff.c\nindex 340c4eb4f7..9f7e4c427d 100644\n--- a/userdiff.c\n+++ b/userdiff.c\n@@ -336,6 +336,13 @@ PATTERNS(\"scheme\",\n         \"|([^][)(}{[ \\t])+\"),\n PATTERNS(\"tex\", \"^(\\\\\\\\((sub)*section|chapter|part)\\\\*{0,1}\\\\{.*)$\",\n         \"\\\\\\\\[a-zA-Z@]+|\\\\\\\\.|([a-zA-Z0-9]|[^\\x01-\\x7f])+\"),\n+PATTERNS(\"verilog\",\n+             \"^[ \\t]*((module|task|function)[ \\t].*)$\",\n+             /* -- */\n+             \"[a-zA-Z_][a-zA-Z0-9_]*\"  \n+             \"|[0-9]+'[bdh][0-9a-fA-F_]+\"  \n+             \"|<=|>=|==|!=|\\\\|\\\\||&&|<<|>>\"\n+    ),\n { .name = \"default\", .binary = -1 },\n };\n #undef PATTERNS"},{"id":"514928","messageId":"Z-FbdgY6ZU2mQGY2@pks.im","threadId":"63110","inReplyTo":"SEZPR01MB5486F5B360F1DFA607C69F37A3D32@SEZPR01MB5486.apcprd01.prod.exchangelabs.com","subject":"Re: [GSoC][Patch] Add more builtin patterns for userdiff: Add builtin patterns for Verilog","fromName":"Patrick Steinhardt","fromEmail":"ps@pks.im","sentAt":"2025-03-24T13:17:42Z","receivedAt":"2025-03-24T13:17:46Z","isPatch":true,"sender":{"key":"ps@pks.im","avatar":"https://avatars.githubusercontent.com/u/4056630?v=4"},"body":"Hi Li,\n\nOn Thu, Mar 13, 2025 at 02:23:05PM +0000, li li wrote:\n> Add Verilog built-in to userdiff.c. I read the code and checked the previous mailing list. I found that if I want git to recognize Verilog syntax, I need to add Verilog regular expressions to the userdiff_driver array of userdiff.c and modify the .gitattributes file.\n> Yes, I did it.\n> The next step is to write test cases and submit patches.\n> I am not sure if this is in line with the development process specifications. Maybe I should make some adjustments. If so, please let me know.\n\nI would recommend to read up on how to submit patches in\n\"Documentation/SubmittingPatches\". There's also\n\"Documentation/MyFirstContribution.adoc\" to give more background on how\nthings work in our community.\n\n> diff --git a/.gitattributes b/.gitattributes\n> index 43fa883a84..8aac8574f1 100644\n> --- a/.gitattributes\n> +++ b/.gitattributes\n> @@ -6,6 +6,7 @@\n>  *.pm text eol=lf diff=perl\n>  *.py text eol=lf diff=python\n>  *.bat text eol=crlf\n> +*.v text eof=lf diff=verilog\n\nThe gitattributes file is specific to files stored in this particular\nproject, and we don't have any Verilog files in our tree. So this change\nshould be dropped.\n\n>  CODE_OF_CONDUCT.md -whitespace\n>  /Documentation/**/*.adoc text eol=lf\n>  /command-list.txt text eol=lf\n> diff --git a/userdiff.c b/userdiff.c\n> index 340c4eb4f7..9f7e4c427d 100644\n> --- a/userdiff.c\n> +++ b/userdiff.c\n> @@ -336,6 +336,13 @@ PATTERNS(\"scheme\",\n>          \"|([^][)(}{[ \\t])+\"),\n>  PATTERNS(\"tex\", \"^(\\\\\\\\((sub)*section|chapter|part)\\\\*{0,1}\\\\{.*)$\",\n>          \"\\\\\\\\[a-zA-Z@]+|\\\\\\\\.|([a-zA-Z0-9]|[^\\x01-\\x7f])+\"),\n> +PATTERNS(\"verilog\",\n> +             \"^[ \\t]*((module|task|function)[ \\t].*)$\",\n> +             /* -- */\n> +             \"[a-zA-Z_][a-zA-Z0-9_]*\"  \n> +             \"|[0-9]+'[bdh][0-9a-fA-F_]+\"  \n> +             \"|<=|>=|==|!=|\\\\|\\\\||&&|<<|>>\"\n> +    ),\n>  { .name = \"default\", .binary = -1 },\n>  };\n>  #undef PATTERNS\n\nI cannot say much about this hunk as I've never written or even read any\nVerilog :)\n\nPatrick\n\n[1]: https://gitgitgadget.github.io/\n"}]}