{"thread":{"id":"20562","subject":"[PATCH 2/3] block-sha1: split the different \"hacks\" to be individually selected","startedAt":"2009-08-12T19:46:41Z","lastAt":"2009-08-12T19:46:41Z","messageCount":1,"participants":["Nicolas Pitre"],"isPatch":true,"patchVersion":1,"patchTotal":3},"messages":[{"id":"120442","messageId":"alpine.LFD.2.00.0908121545530.10633@xanadu.home","threadId":"20562","inReplyTo":null,"subject":"[PATCH 2/3] block-sha1: split the different \"hacks\" to be individually selected","fromName":"Nicolas Pitre","fromEmail":"nico@cam.org","sentAt":"2009-08-12T19:46:41Z","receivedAt":"2009-08-12T19:46:41Z","isPatch":true,"sender":{"key":"nico@fluxnic.net","avatar":"https://avatars.githubusercontent.com/u/702790?v=4"},"body":"\nThis is to make it easier for them to be selected individually depending\non the architecture instead of the other way around i.e. having each\narchitecture select a list of hacks up front.  That makes for clearer\ndocumentation as well.\n\nSigned-off-by: Nicolas Pitre <nico@cam.org>\n---\n block-sha1/sha1.c |   23 ++++++++++++++++++-----\n 1 files changed, 18 insertions(+), 5 deletions(-)\n\ndiff --git a/block-sha1/sha1.c b/block-sha1/sha1.c\nindex c3f1ae5..67c9bd0 100644\n--- a/block-sha1/sha1.c\n+++ b/block-sha1/sha1.c\n@@ -11,10 +11,16 @@\n \n #if defined(__i386__) || defined(__x86_64__)\n \n+/*\n+ * Force usage of rol or ror by selecting the one with the smaller constant.\n+ * It _can_ generate slightly smaller code (a constant of 1 is special), but\n+ * perhaps more importantly it's possibly faster on any uarch that does a\n+ * rotate with a loop.\n+ */\n+\n #define SHA_ASM(op, x, n) ({ unsigned int __res; __asm__(op \" %1,%0\":\"=r\" (__res):\"i\" (n), \"0\" (x)); __res; })\n #define SHA_ROL(x,n)\tSHA_ASM(\"rol\", x, n)\n #define SHA_ROR(x,n)\tSHA_ASM(\"ror\", x, n)\n-#define SMALL_REGISTER_SET\n \n #else\n \n@@ -24,9 +30,6 @@\n \n #endif\n \n-/* This \"rolls\" over the 512-bit array */\n-#define W(x) (array[(x)&15])\n-\n /*\n  * If you have 32 registers or more, the compiler can (and should)\n  * try to change the array[] accesses into registers. However, on\n@@ -43,13 +46,23 @@\n  * Ben Herrenschmidt reports that on PPC, the C version comes close\n  * to the optimized asm with this (ie on PPC you don't want that\n  * 'volatile', since there are lots of registers).\n+ *\n+ * On ARM we get the best code generation by forcing a full memory barrier\n+ * between each SHA_ROUND, otherwise gcc happily get wild with spilling and\n+ * the stack frame size simply explode and performance goes down the drain.\n  */\n-#ifdef SMALL_REGISTER_SET\n+\n+#if defined(__i386__) || defined(__x86_64__)\n   #define setW(x, val) (*(volatile unsigned int *)&W(x) = (val))\n+#elif defined(__arm__)\n+  #define setW(x, val) do { W(x) = (val); __asm__(\"\":::\"memory\"); } while (0)\n #else\n   #define setW(x, val) (W(x) = (val))\n #endif\n \n+/* This \"rolls\" over the 512-bit array */\n+#define W(x) (array[(x)&15])\n+\n /*\n  * Where do we get the source from? The first 16 iterations get it from\n  * the input data, the next mix it from the 512-bit array.\n-- \n1.6.4.189.g282fa\n"}]}