{"thread":{"id":"10765","subject":"Re: [PATCH 3/9] msm: timer support using the GPT and DGT timers","startedAt":"2007-11-09T13:39:30Z","lastAt":"2007-11-09T13:39:30Z","messageCount":1,"participants":["Brian Swetland"],"isPatch":true,"patchVersion":1,"patchTotal":9},"messages":[{"id":"59043","messageId":"20071109133930.GA24962@bulgaria","threadId":"10765","inReplyTo":"20071109131930.GA19343@bre-cln-ukleine.digi.com","subject":"Re: [PATCH 3/9] msm: timer support using the GPT and DGT timers","fromName":"Brian Swetland","fromEmail":"swetland@google.com","sentAt":"2007-11-09T13:39:30Z","receivedAt":"2007-11-09T13:39:30Z","isPatch":true,"sender":{"key":"swetland@google.com","avatar":"https://gravatar.com/avatar/b26b7c772097c55d8febb0fc027dd2ef577a05994a321819f49ab3c9153ac8b1?d=mp&s=160"},"body":"[Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>]\n> \n> Hello Brian,\n> \n> [adding git ML to Cc:]\n> \n> > > \tContent-Type: text/plain; charset=utf-8\n> > > \tContent-Transfer-Encoding: 8bit\n> > \n> > Mine do not seem to.\n> I think they are only generated if the content contains non-ASCII.  So\n> the attached example isn't very helpful.\n\nLooking at more of the patches (sorry about sending one not exhibiting\nthe problem -- I picked a small one, forgetting that not all of them\nhad Arve's name as the author), it looks like the body is plain 7bit\nascii, but the From header has the utf-8 content:\n\n>From 0ac8027053bb686c19a412f0f22f4a305a77ab59 Mon Sep 17 00:00:00 2001\nFrom: =?utf-8?q?Arve=20Hj=C3=B8nnev=C3=A5g?= <arve@android.com>\nDate: Wed, 7 Nov 2007 22:17:29 -0800\nSubject: [PATCH 3/9] msm: timer support using the GPT and DGT timers\n\nWhen sent with git-send-email, the From: line above ended up in the\nmessage, unescaped as utf-8 text, but the generated email itself did\nnot have any encoding specified.  I didn't \n\nAttached is the original patch and the message that resulted when I\nused git-send-email to mail the patch to myself.\n\nBrian\n\n\n>From 0ac8027053bb686c19a412f0f22f4a305a77ab59 Mon Sep 17 00:00:00 2001\nFrom: =?utf-8?q?Arve=20Hj=C3=B8nnev=C3=A5g?= <arve@android.com>\nDate: Wed, 7 Nov 2007 22:17:29 -0800\nSubject: [PATCH 3/9] msm: timer support using the GPT and DGT timers\n\nSigned-off-by: Brian Swetland <swetland@android.com>\n---\n arch/arm/mach-msm/timer.c |  205 +++++++++++++++++++++++++++++++++++++++++++++\n 1 files changed, 205 insertions(+), 0 deletions(-)\n create mode 100644 arch/arm/mach-msm/timer.c\n\ndiff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c\nnew file mode 100644\nindex 0000000..0781a16\n--- /dev/null\n+++ b/arch/arm/mach-msm/timer.c\n@@ -0,0 +1,205 @@\n+/* linux/arch/arm/mach-msm/timer.c\n+**\n+** Copyright (C) 2007 Google, Inc.\n+**\n+** This software is licensed under the terms of the GNU General Public\n+** License version 2, as published by the Free Software Foundation, and\n+** may be copied, distributed, and modified under those terms.\n+**\n+** This program is distributed in the hope that it will be useful,\n+** but WITHOUT ANY WARRANTY; without even the implied warranty of\n+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+** GNU General Public License for more details.\n+**\n+*/\n+\n+#include <linux/init.h>\n+#include <linux/time.h>\n+#include <linux/interrupt.h>\n+#include <linux/irq.h>\n+#include <linux/clk.h>\n+#include <linux/clockchips.h>\n+#include <linux/delay.h>\n+\n+#include <asm/mach/time.h>\n+#include <asm/arch/msm_iomap.h>\n+\n+#include <asm/io.h>\n+\n+#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)\n+#define MSM_DGT_SHIFT (5)\n+\n+#define TIMER_MATCH_VAL         0x0000\n+#define TIMER_COUNT_VAL         0x0004\n+#define TIMER_ENABLE            0x0008\n+#define TIMER_ENABLE_CLR_ON_MATCH_EN    2\n+#define TIMER_ENABLE_EN                 1\n+#define TIMER_CLEAR             0x000C\n+\n+#define CSR_PROTECTION          0x0020\n+#define CSR_PROTECTION_EN               1\n+\n+#define GPT_HZ 32768\n+#define DGT_HZ 19200000 // 19.2 MHz or 600 KHz after shift\n+\n+struct msm_clock {\n+\tstruct clock_event_device   clockevent;\n+\tstruct clocksource          clocksource;\n+\tstruct irqaction            irq;\n+\tuint32_t                    regbase;\n+\tuint32_t                    freq;\n+\tuint32_t                    shift;\n+};\n+\n+static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)\n+{\n+\tstruct clock_event_device *evt = dev_id;\n+\tevt->event_handler(evt);\n+\treturn IRQ_HANDLED;\n+}\n+\n+static cycle_t msm_gpt_read(void)\n+{\n+\treturn msm_readl(MSM_GPT_BASE + TIMER_COUNT_VAL);\n+}\n+\n+static cycle_t msm_dgt_read(void)\n+{\n+\treturn msm_readl(MSM_DGT_BASE + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT;\n+}\n+\n+static int msm_timer_set_next_event(unsigned long cycles,\n+\t\t\t\t    struct clock_event_device *evt)\n+{\n+\tstruct msm_clock *clock = container_of(evt, struct msm_clock, clockevent);\n+\tuint32_t now = msm_readl(clock->regbase + TIMER_COUNT_VAL);\n+\tuint32_t alarm = now + (cycles << clock->shift);\n+\tint late;\n+\n+\tmsm_writel(alarm, clock->regbase + TIMER_MATCH_VAL);\n+\tnow = msm_readl(clock->regbase + TIMER_COUNT_VAL);\n+\tlate = now - alarm;\n+\tif(late >= (-2 << clock->shift) && late < DGT_HZ*5) {\n+\t\tprintk(KERN_NOTICE \"msm_timer_set_next_event(%lu) clock %s, \"\n+\t\t       \"alarm already expired, now %x, alarm %x, late %d\\n\",\n+\t\t       cycles, clock->clockevent.name, now, alarm, late);\n+\t\treturn -ETIME;\n+\t}\n+\treturn 0;\n+}\n+\n+static void msm_timer_set_mode(enum clock_event_mode mode,\n+\t\t\t      struct clock_event_device *evt)\n+{\n+\tstruct msm_clock *clock = container_of(evt, struct msm_clock, clockevent);\n+\tswitch (mode) {\n+\tcase CLOCK_EVT_MODE_RESUME:\n+\tcase CLOCK_EVT_MODE_PERIODIC:\n+\t\tbreak;\n+\tcase CLOCK_EVT_MODE_ONESHOT:\n+\t\tmsm_writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);\n+\t\tbreak;\n+\tcase CLOCK_EVT_MODE_UNUSED:\n+\tcase CLOCK_EVT_MODE_SHUTDOWN:\n+\t\tmsm_writel(0, clock->regbase + TIMER_ENABLE);\n+\t\tbreak;\n+\t}\n+}\n+\n+static struct msm_clock msm_clocks[] = {\n+\t{\n+\t\t.clockevent = {\n+\t\t\t.name           = \"gp_timer\",\n+\t\t\t.features       = CLOCK_EVT_FEAT_ONESHOT,\n+\t\t\t.shift          = 32,\n+\t\t\t.rating         = 200,\n+\t\t\t.set_next_event = msm_timer_set_next_event,\n+\t\t\t.set_mode       = msm_timer_set_mode,\n+\t\t},\n+\t\t.clocksource = {\n+\t\t\t.name           = \"gp_timer\",\n+\t\t\t.rating         = 200,\n+\t\t\t.read           = msm_gpt_read,\n+\t\t\t.mask           = CLOCKSOURCE_MASK(32),\n+\t\t\t.shift          = 24,\n+\t\t\t.flags          = CLOCK_SOURCE_IS_CONTINUOUS,\n+\t\t},\n+\t\t.irq = {\n+\t\t\t.name    = \"gp_timer\",\n+\t\t\t.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,\n+\t\t\t.handler = msm_timer_interrupt,\n+\t\t\t.dev_id  = &msm_clocks[0].clockevent,\n+\t\t\t.irq     = INT_GP_TIMER_EXP\n+\t\t},\n+\t\t.regbase = MSM_GPT_BASE,\n+\t\t.freq = GPT_HZ\n+\t},\n+\t{\n+\t\t.clockevent = {\n+\t\t\t.name           = \"dg_timer\",\n+\t\t\t.features       = CLOCK_EVT_FEAT_ONESHOT,\n+\t\t\t.shift          = 32 + MSM_DGT_SHIFT,\n+\t\t\t.rating         = 300,\n+\t\t\t.set_next_event = msm_timer_set_next_event,\n+\t\t\t.set_mode       = msm_timer_set_mode,\n+\t\t},\n+\t\t.clocksource = {\n+\t\t\t.name           = \"dg_timer\",\n+\t\t\t.rating         = 300,\n+\t\t\t.read           = msm_dgt_read,\n+\t\t\t.mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),\n+\t\t\t.shift          = 24 - MSM_DGT_SHIFT,\n+\t\t\t.flags          = CLOCK_SOURCE_IS_CONTINUOUS,\n+\t\t},\n+\t\t.irq = {\n+\t\t\t.name    = \"dg_timer\",\n+\t\t\t.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,\n+\t\t\t.handler = msm_timer_interrupt,\n+\t\t\t.dev_id  = &msm_clocks[1].clockevent,\n+\t\t\t.irq     = INT_DEBUG_TIMER_EXP\n+\t\t},\n+\t\t.regbase = MSM_DGT_BASE,\n+\t\t.freq = DGT_HZ >> MSM_DGT_SHIFT,\n+\t\t.shift = MSM_DGT_SHIFT\n+\t}\n+};\n+\n+static void /*__init*/ msm_timer_init(void)\n+{\n+\tint i;\n+\tint res;\n+\tprintk(\"msm_timer_init()\\n\");\n+\n+\tfor(i = 0; i < ARRAY_SIZE(msm_clocks); i++) {\n+\t\tstruct msm_clock *clock = &msm_clocks[i];\n+\t\tstruct clock_event_device *ce = &clock->clockevent;\n+\t\tstruct clocksource *cs = &clock->clocksource;\n+\t\tmsm_writel(0, clock->regbase + TIMER_ENABLE);\n+\t\tmsm_writel(0, clock->regbase + TIMER_CLEAR);\n+\t\tmsm_writel(~0, clock->regbase + TIMER_MATCH_VAL);\n+\n+\t\tce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);\n+\t\t// allow at least 10 seconds to notice that the timer wrapped\n+\t\tce->max_delta_ns =\n+\t\t\tclockevent_delta2ns(0xf0000000 >> clock->shift, ce);\n+\t\tce->min_delta_ns = clockevent_delta2ns(4, ce); // 4 gets rounded down to 3\n+\t\tce->cpumask = cpumask_of_cpu(0);\n+\n+\t\tcs->mult = clocksource_hz2mult(clock->freq,cs->shift);\n+\t\tres = clocksource_register(cs);\n+\t\tif(res)\n+\t\t\tprintk(KERN_ERR \"msm_timer_init: clocksource_register \"\n+\t\t\t       \"failed for %s\\n\", cs->name);\n+\n+\t\tres = setup_irq(clock->irq.irq, &clock->irq);\n+\t\tif(res)\n+\t\t\tprintk(KERN_ERR \"msm_timer_init: setup_irq \"\n+\t\t\t       \"failed for %s\\n\", cs->name);\n+\n+\t\tclockevents_register_device(ce);\n+\t}\n+}\n+\n+struct sys_timer msm_timer = {\n+\t.init = msm_timer_init\n+};\n-- \n1.5.3.1\n\n\n\n>From swetland@google.com Fri Nov  9 05:35:00 2007\nReturn-Path: <swetland@google.com>\nReceived: from wpck26.suw.corp.google.com [172.24.219.218]\n\tby bulgaria with IMAP (fetchmail-6.3.6)\n\tfor <swetland@localhost> (single-drop); Fri, 09 Nov 2007 05:35:00 -0800 (PST)\nReceived: from wpck26.suw.corp.google.com ([unix socket])\n\t by imap4.corp.google.com (Cyrus v2.2.12-Invoca-RPM-2.2.12-1gg2) with LMTPA;\n\t Fri, 09 Nov 2007 05:35:04 -0800\nX-Sieve: CMU Sieve 2.2\nReceived: from zps35.corp.google.com (zps35.corp.google.com [172.25.146.35])\n\tby wpck26.suw.corp.google.com with ESMTP id lA9DZ4Ou025468\n\tfor <swetland@wpck26.suw.corp.google.com>; Fri, 9 Nov 2007 05:35:04 -0800\nReceived: from bulgaria (bulgaria.corp.google.com [172.18.102.38])\n\tby zps35.corp.google.com with ESMTP id lA9DYufb029971;\n\tFri, 9 Nov 2007 05:34:56 -0800\nReceived: by bulgaria (Postfix, from userid 1000)\n\tid 5618E8F45E; Fri,  9 Nov 2007 05:34:46 -0800 (PST)\nFrom: swetland@google.com\nTo: swetland@google.com\nCc: =?utf-8?q?Arve=20Hj=C3=B8nnev=C3=A5g?= <arve@android.com>,\n        Brian Swetland <swetland@android.com>\nSubject: [PATCH 3/9] msm: timer support using the GPT and DGT timers\nDate: Fri,  9 Nov 2007 05:34:46 -0800\nMessage-Id: <11946152862759-git-send-email-swetland@frotz.net>\nX-Mailer: git-send-email 1.5.3.1\nStatus: RO\nContent-Length: 6551\n\nFrom: Arve Hjønnevåg <arve@android.com>\n\nSigned-off-by: Brian Swetland <swetland@android.com>\n---\n arch/arm/mach-msm/timer.c |  205 +++++++++++++++++++++++++++++++++++++++++++++\n 1 files changed, 205 insertions(+), 0 deletions(-)\n create mode 100644 arch/arm/mach-msm/timer.c\n\ndiff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c\nnew file mode 100644\nindex 0000000..0781a16\n--- /dev/null\n+++ b/arch/arm/mach-msm/timer.c\n@@ -0,0 +1,205 @@\n+/* linux/arch/arm/mach-msm/timer.c\n+**\n+** Copyright (C) 2007 Google, Inc.\n+**\n+** This software is licensed under the terms of the GNU General Public\n+** License version 2, as published by the Free Software Foundation, and\n+** may be copied, distributed, and modified under those terms.\n+**\n+** This program is distributed in the hope that it will be useful,\n+** but WITHOUT ANY WARRANTY; without even the implied warranty of\n+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+** GNU General Public License for more details.\n+**\n+*/\n+\n+#include <linux/init.h>\n+#include <linux/time.h>\n+#include <linux/interrupt.h>\n+#include <linux/irq.h>\n+#include <linux/clk.h>\n+#include <linux/clockchips.h>\n+#include <linux/delay.h>\n+\n+#include <asm/mach/time.h>\n+#include <asm/arch/msm_iomap.h>\n+\n+#include <asm/io.h>\n+\n+#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)\n+#define MSM_DGT_SHIFT (5)\n+\n+#define TIMER_MATCH_VAL         0x0000\n+#define TIMER_COUNT_VAL         0x0004\n+#define TIMER_ENABLE            0x0008\n+#define TIMER_ENABLE_CLR_ON_MATCH_EN    2\n+#define TIMER_ENABLE_EN                 1\n+#define TIMER_CLEAR             0x000C\n+\n+#define CSR_PROTECTION          0x0020\n+#define CSR_PROTECTION_EN               1\n+\n+#define GPT_HZ 32768\n+#define DGT_HZ 19200000 // 19.2 MHz or 600 KHz after shift\n+\n+struct msm_clock {\n+\tstruct clock_event_device   clockevent;\n+\tstruct clocksource          clocksource;\n+\tstruct irqaction            irq;\n+\tuint32_t                    regbase;\n+\tuint32_t                    freq;\n+\tuint32_t                    shift;\n+};\n+\n+static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)\n+{\n+\tstruct clock_event_device *evt = dev_id;\n+\tevt->event_handler(evt);\n+\treturn IRQ_HANDLED;\n+}\n+\n+static cycle_t msm_gpt_read(void)\n+{\n+\treturn msm_readl(MSM_GPT_BASE + TIMER_COUNT_VAL);\n+}\n+\n+static cycle_t msm_dgt_read(void)\n+{\n+\treturn msm_readl(MSM_DGT_BASE + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT;\n+}\n+\n+static int msm_timer_set_next_event(unsigned long cycles,\n+\t\t\t\t    struct clock_event_device *evt)\n+{\n+\tstruct msm_clock *clock = container_of(evt, struct msm_clock, clockevent);\n+\tuint32_t now = msm_readl(clock->regbase + TIMER_COUNT_VAL);\n+\tuint32_t alarm = now + (cycles << clock->shift);\n+\tint late;\n+\n+\tmsm_writel(alarm, clock->regbase + TIMER_MATCH_VAL);\n+\tnow = msm_readl(clock->regbase + TIMER_COUNT_VAL);\n+\tlate = now - alarm;\n+\tif(late >= (-2 << clock->shift) && late < DGT_HZ*5) {\n+\t\tprintk(KERN_NOTICE \"msm_timer_set_next_event(%lu) clock %s, \"\n+\t\t       \"alarm already expired, now %x, alarm %x, late %d\\n\",\n+\t\t       cycles, clock->clockevent.name, now, alarm, late);\n+\t\treturn -ETIME;\n+\t}\n+\treturn 0;\n+}\n+\n+static void msm_timer_set_mode(enum clock_event_mode mode,\n+\t\t\t      struct clock_event_device *evt)\n+{\n+\tstruct msm_clock *clock = container_of(evt, struct msm_clock, clockevent);\n+\tswitch (mode) {\n+\tcase CLOCK_EVT_MODE_RESUME:\n+\tcase CLOCK_EVT_MODE_PERIODIC:\n+\t\tbreak;\n+\tcase CLOCK_EVT_MODE_ONESHOT:\n+\t\tmsm_writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);\n+\t\tbreak;\n+\tcase CLOCK_EVT_MODE_UNUSED:\n+\tcase CLOCK_EVT_MODE_SHUTDOWN:\n+\t\tmsm_writel(0, clock->regbase + TIMER_ENABLE);\n+\t\tbreak;\n+\t}\n+}\n+\n+static struct msm_clock msm_clocks[] = {\n+\t{\n+\t\t.clockevent = {\n+\t\t\t.name           = \"gp_timer\",\n+\t\t\t.features       = CLOCK_EVT_FEAT_ONESHOT,\n+\t\t\t.shift          = 32,\n+\t\t\t.rating         = 200,\n+\t\t\t.set_next_event = msm_timer_set_next_event,\n+\t\t\t.set_mode       = msm_timer_set_mode,\n+\t\t},\n+\t\t.clocksource = {\n+\t\t\t.name           = \"gp_timer\",\n+\t\t\t.rating         = 200,\n+\t\t\t.read           = msm_gpt_read,\n+\t\t\t.mask           = CLOCKSOURCE_MASK(32),\n+\t\t\t.shift          = 24,\n+\t\t\t.flags          = CLOCK_SOURCE_IS_CONTINUOUS,\n+\t\t},\n+\t\t.irq = {\n+\t\t\t.name    = \"gp_timer\",\n+\t\t\t.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,\n+\t\t\t.handler = msm_timer_interrupt,\n+\t\t\t.dev_id  = &msm_clocks[0].clockevent,\n+\t\t\t.irq     = INT_GP_TIMER_EXP\n+\t\t},\n+\t\t.regbase = MSM_GPT_BASE,\n+\t\t.freq = GPT_HZ\n+\t},\n+\t{\n+\t\t.clockevent = {\n+\t\t\t.name           = \"dg_timer\",\n+\t\t\t.features       = CLOCK_EVT_FEAT_ONESHOT,\n+\t\t\t.shift          = 32 + MSM_DGT_SHIFT,\n+\t\t\t.rating         = 300,\n+\t\t\t.set_next_event = msm_timer_set_next_event,\n+\t\t\t.set_mode       = msm_timer_set_mode,\n+\t\t},\n+\t\t.clocksource = {\n+\t\t\t.name           = \"dg_timer\",\n+\t\t\t.rating         = 300,\n+\t\t\t.read           = msm_dgt_read,\n+\t\t\t.mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),\n+\t\t\t.shift          = 24 - MSM_DGT_SHIFT,\n+\t\t\t.flags          = CLOCK_SOURCE_IS_CONTINUOUS,\n+\t\t},\n+\t\t.irq = {\n+\t\t\t.name    = \"dg_timer\",\n+\t\t\t.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,\n+\t\t\t.handler = msm_timer_interrupt,\n+\t\t\t.dev_id  = &msm_clocks[1].clockevent,\n+\t\t\t.irq     = INT_DEBUG_TIMER_EXP\n+\t\t},\n+\t\t.regbase = MSM_DGT_BASE,\n+\t\t.freq = DGT_HZ >> MSM_DGT_SHIFT,\n+\t\t.shift = MSM_DGT_SHIFT\n+\t}\n+};\n+\n+static void /*__init*/ msm_timer_init(void)\n+{\n+\tint i;\n+\tint res;\n+\tprintk(\"msm_timer_init()\\n\");\n+\n+\tfor(i = 0; i < ARRAY_SIZE(msm_clocks); i++) {\n+\t\tstruct msm_clock *clock = &msm_clocks[i];\n+\t\tstruct clock_event_device *ce = &clock->clockevent;\n+\t\tstruct clocksource *cs = &clock->clocksource;\n+\t\tmsm_writel(0, clock->regbase + TIMER_ENABLE);\n+\t\tmsm_writel(0, clock->regbase + TIMER_CLEAR);\n+\t\tmsm_writel(~0, clock->regbase + TIMER_MATCH_VAL);\n+\n+\t\tce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);\n+\t\t// allow at least 10 seconds to notice that the timer wrapped\n+\t\tce->max_delta_ns =\n+\t\t\tclockevent_delta2ns(0xf0000000 >> clock->shift, ce);\n+\t\tce->min_delta_ns = clockevent_delta2ns(4, ce); // 4 gets rounded down to 3\n+\t\tce->cpumask = cpumask_of_cpu(0);\n+\n+\t\tcs->mult = clocksource_hz2mult(clock->freq,cs->shift);\n+\t\tres = clocksource_register(cs);\n+\t\tif(res)\n+\t\t\tprintk(KERN_ERR \"msm_timer_init: clocksource_register \"\n+\t\t\t       \"failed for %s\\n\", cs->name);\n+\n+\t\tres = setup_irq(clock->irq.irq, &clock->irq);\n+\t\tif(res)\n+\t\t\tprintk(KERN_ERR \"msm_timer_init: setup_irq \"\n+\t\t\t       \"failed for %s\\n\", cs->name);\n+\n+\t\tclockevents_register_device(ce);\n+\t}\n+}\n+\n+struct sys_timer msm_timer = {\n+\t.init = msm_timer_init\n+};\n-- \n1.5.3.1\n\n\n"}]}